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Iran Conflict 2026
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€659m for four fabs, none at the edge

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14:57UTC

The European Commission approved €659m of German state aid on 14 July for four semiconductor plants, the largest €353m to Element 3-5 for silicon-carbide wafers. Every one sits at the power and analog layer, not leading-edge logic.

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Key takeaway

Germany's four newly-funded fabs build power and analog chips, not the leading-edge logic Europe lacks.

The European Commission approved €659m of German state aid on 14 July for four first-of-a-kind semiconductor plants under the European Chips Act, the EU's 2023 framework for subsidising domestic chip production. 1 The money splits four ways: Element 3-5 takes €353m for silicon-carbide (SiC) epitaxial wafers in North Rhine-Westphalia; Vishay takes €214m for power metal-oxide-semiconductor field-effect transistors (MOSFETs) in Schleswig-Holstein; KLA-Tencor's metrology arm takes €74.4m for chip quality-control measurement equipment in Hesse; and KETEK takes €17.9m for specialised industrial chips in Bavaria.

These are projects 15 to 18 under the Chips Act, taking cumulative approved support across member states to roughly €14.2bn. Every one sits at the power, analog and metrology layer where Europe already holds ground, not at the leading-edge logic layer where it does not. Silicon carbide and power MOSFETs handle high-voltage switching in electric vehicles and grid hardware, a tier of the value chain well away from the sub-7-nanometre logic that runs AI and smartphones.

None of the four plants is in Dresden, keeping this tranche distinct from Infineon's €5bn Smart Power Fab that opened there on 2 July . European fabs have already shown they can run a sovereign flow end to end at this tier, as GlobalFoundries and Qualinx did at Dresden last month .

Element 3-5's silicon-carbide wafers and Vishay's power transistors add capacity Europe can use. They do not move the number The Commission most wants moved, which its own Digital Decade scorecard put at 9% of global chip output against a 20% target .

Deep Analysis

In plain English

The EU's Chips Act is a subsidy programme meant to reduce Europe's dependence on Asian and American chip factories. On 14 July, the European Commission approved €659m of German state aid split across four projects: money for silicon-carbide wafers, used in electric vehicles and renewable energy, power transistors, chip-testing equipment, and specialised industrial chips, spread across North Rhine-Westphalia, Schleswig-Holstein, Bavaria and Hesse. None of these make the most advanced chips that power the newest AI systems; that manufacturing stays concentrated in Taiwan, South Korea and the US. Instead, the money targets areas where German and European firms already have real expertise: power electronics and specialised industrial chips, not the cutting edge.

Deep Analysis
Root Causes

Leading-edge logic fabrication requires EUV tools only ASML makes and packaging expertise concentrated in Taiwan and South Korea, a chain Europe cannot shortcut with state aid alone.

Europe's realistic near-term edge sits upstream, in power and analogue chips such as silicon carbide and MOSFETs, where firms like Infineon, STMicro and Vishay already compete globally. The €659m follows that comparative-advantage logic rather than chasing the leading edge, a gap COREPER's $40bn Pax Silica commitment effectively concedes by buying US chips instead.

What could happen next?
  • Opportunity

    Directing aid to power and analogue segments where German firms already lead could compound Europe's existing comparative advantage rather than chase an unwinnable leading-edge race.

  • Risk

    None of the four projects address the leading-edge logic dependency the $40bn Pax Silica chip-purchase commitment (ID:4094) is meant to offset through US imports instead.

First Reported In

Update #12 · ASML's tool boom skips Europe's logic gap

European Commission· 16 Jul 2026
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Causes and effects
This Event
€659m for four fabs, none at the edge
Europe funded the chip layers where it already competes, leaving the leading-edge logic gap that defines its dependence untouched.
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